1. Field of the Invention
The invention pertains to semiconductor processing methods and semiconductor constructions. In particular aspects, the invention pertains to a method and apparatus to integrate and fabricate coplanar dielectrically isolated regions of different semiconductor materials on a hybrid monolithic substrate.
2. Description of Related Art
Semiconductor devices fabricated on silicon (group IV) substrates are abundantly employed in high-volume microelectronics where high-density, high-performance, and low-power consumption are simultaneously desired. CMOS, bipolar, and BICMOS technologies fabricated on either bulk silicon or silicon on insulator (SOI) substrates are commonly used in microprocessor, memory, and analog electronics applications.
In addition to Silicon, there is a need for other types of group IV semiconductors such as Ge, SiGe and SiC for certain niche applications. For example, Germanium offers narrower bandgap and higher mobility than silicon. Silicon carbide is employed in products required to operate in harsh (e.g., hot) environments. However, group IV semiconductor devices have not been widely used for optoelectronics due to their indirect band gap structure which can result in low photo-emission efficiency.
Optoelectronic devices that are commonly used include III-V and II-VI compound semiconductor materials such as GaAs, InP, InGaP, InAs, AlGaAs, GaN, GaInAs, and AlGaSb. These compound semiconductor materials possess direct band gap properties and high photo-emission efficiency. Further, electronic properties of compound semiconductor materials make them ideal candidates for optoelectronics products such as LEDs, VCELs, photovoltaic devices, as well as high performance microwave devices such as PIN diodes, and heterojunction bipolar transistors (HBTs).
Designers, however, face persistent problems in integrating electronic and optoelectronic devices from multiple types of semiconductor materials into a single compact, high-performance and cost effective package.
In one approach to solve the above-noted problem, both silicon-based and compound semiconductor based optoelectronic integrated circuit chips are combined into a single package. The individual chips are interconnected by wiring, and optical waveguides formed on a common insulating or semi-insulating substrate are disclosed in U.S. Pat. No. 5,611,008, the entire contents of which are incorporated herein by reference.
The above-noted approach often suffers from performance penalties due to relatively long interconnections (e.g., on-chip interconnections) among the various types of integrated-circuit chips. Further, alignment of lasers to on-substrate fiberoptics can be a challenge. Other drawbacks include severe density penalty as scalability of interconnections on the common substrate falls far short of what can be achieved on individual IC chips. In addition to the above, the cost of manufacturing multi-chip substrates is high relative to the cost of manufacture single IC chips.
In another approach, a layer of mono-crystalline compound semiconductor (e.g. GaAs) is epitaxially grown directly on a silicon substrate. No intervening insulating layer exists between the silicon substrate and the grown layer as illustrated in U.S. Pat. No. 5,081,062, the entire contents of which are incorporated herein by reference. The resulting structure of this approach can complicate the process of isolating silicon electronics from compound semiconductor regions. Furthermore, regions of different semiconductor material formed using this approach are not coplanar, thereby resulting in depth of focus and other processing issues.
Another solution to the above-noted problem epitaxially grows a plurality of material layers including intervening strain relieving buffer and transition layers on a group IV semiconductor (e.g. Si) substrate having trenches as in U.S. Pat. No. 6,673,667, the entire contents of which are incorporated herein by reference. A monocrystalline III-V compound semiconductor (e.g. GaAs, AlGaAs) is then epitaxially grown over the buffer layers. Although, the patterned template layer is used to define the pattern of the top compound semiconductor layer, no substantial vertical isolation is achieved.
Therefore, there is a need to overcome the above-noted problems.